Worldwide interest in light-emitting diode (LED) technology has rapidly increased over the past two decades. Starting with inorganic LEDs developed in the 60 s, they have found their way into numerous lighting, signaling, and display applications, such as, automotive lighting, architectural lighting, flashlights, and backlights for LCD-based displays. Since the turn of the century they have started to appear in more mainstream lighting applications, which as a result of their long life and very high efficacy, will result in significant savings in energy usage. This set of applications include traffic signaling lights, street lights, and most recently, residential lighting.
In spite of the deepening penetration of inorganic LEDs into mainstream lighting, unresolved issues still remain, such as, high cost, poor color, and sub-desirable efficiency. Overall there are two ways for creating white LEDs (M. Krames et al., J. Display Technol. 3, 160 (2007)), combining blue, green, and red LEDs to form white LED arrays or combining a blue LED with appropriate down conversion phosphors to create a white light source. The first way yields a higher overall efficiency. Despite very high internal quantum efficiencies for red and blue LEDs of approximately 90 and 70%, respectively, the IQE of green LEDs at the desirable wavelengths of 540-560 nm is below 10%. This “green gap” issue has been recognized for many years (large strain develops in the active region as a result of incorporating sufficient indium in the GaN in order to form green emitting InGaN) and despite numerous efforts, still remains largely unresolved. Combining blue GaN LEDs with appropriate phosphors has recently yielded white LEDs with efficacies over 120 Lumens/Watt. Unfortunately, the correlated color temperature (CCT) of the corresponding white is typically high (>6000 K), yielding a cold light which lacks sufficient red response. Both inorganic LED approaches for white light, as of today, are approximately a factor of 100 too costly to engender significant market penetration into the residential market without significant government subsidies or incentives.
As discussed above, many issues still remain for inorganic LEDs (to be called LEDs) in lighting applications. Focusing on color-mixed LEDs (combining red, green, and blue LEDs), the two pressing issues are high cost and the sub-par performance of green LEDs. A large part of the high cost is associated with conventional LEDs grown on crystalline substrates, specifically sapphire or SiC for blue and green LEDs and GaAs for red LEDs.
Recently, there has been significant research activity towards creating nanowire-based LEDs, where the nanowires are grown using metal-organic vapor phase epitaxy (MOVPE) techniques by either a templated (S. Hersee et al., Electron. Lett. 45, 75 (2009)) or vapor liquid solid (VLS) approach (S. Lee et al. Philosophical Magazine 87, 2105 (2007)). The advantages of employing nanowires as LED elements are that they can be grown on inexpensive substrates (such as glass) and the amount of lattice mismatch that can be tolerated between LED layers is significantly higher when the crystalline material is a 20-100 nm thick nanowire as compared to bulk heterostructure growth (D. Zubia et al., J. Appl. Phys. 85, 6492 (1999)). However, device integration is a challenge with using nanowires as LED elements.
Researchers have been investigating forming LEDs, and other electronic devices, from nanowires by transferring the nanowires to a separate device substrate. The most common methods involve transferring nanowires so that they are horizontal, or parallel to the plane of the substrate, using techniques such as contact printing (Z. Fan et al, Nano Lett., 8, 1, 20 (2008)). There are many challenges in forming devices from horizontal nanowire arrays, including nanowire alignment and electrically contacting the wires to form useful circuits.
In answer to the challenges of horizontal nanowire array integration, there has been recent work to vertically integrate nanowires into electronic devices. Vertically integrated nanowire devices have been formed on the nanowire growth substrate by filling the spaces between the as-grown wires with a coatable dielectric material, such as a polymer or spin-on-glass, and subsequently adding electrodes (E. Latu-Romain, et al, Nanotechnology, 19 (2008)). One disadvantage of forming devices in this manner is that is difficult to make direct electrical contact to both ends of the nanowires.
There have been some advances in the photovoltaic field in forming structures containing vertically aligned silicon wires by removing the silicon wires from the growth substrate. Self-supporting films of silicon wires having diameters of 1.5-2 um and lengths of 75-100 um embedded within a PDMS matrix have recently been demonstrated (K. Plass, et al, Adv. Mater., 21, 325-328, (2009)). These films were formed by coating a PDMS solution over the growth substrate and then peeling the resultant embedded wire film from the substrate. Test devices have been formed from these films that demonstrate that electrical contact can be made to both ends of the wires. The article suggests that these films could be used to form solar cells by depositing a transparent electrode on a front surface, and a reflective metal electrode on the back surface of the film (Kelzenberg, M, et al, Proc. 34th IEEE PVSC (2009)). However, unlike the nanowires which are useful for LED devices, the Si wires useful for these photovoltaic devices have diameters that are a micron or greater and are many times longer than typical nanowires. A challenge still remains for integrating true nanowires that have submicron diameters of 5 to 500 nanometers with lengths of 2 to 10 microns, since these films would not be self supporting.
A prior art vertically integrated silicon wire device 255 is shown in FIG. 2. In the figure, a first electrode is 205, a second electrode is 210, a silicon semiconductor wire is 250 and a polymer dielectric is 230. The silicon wires 250 have diameters of 1.5-5 um and lengths of 75-100 um. The polymer dielectric 230 is PDMS. (K. Plass, et al, Adv. Mater., 21, 325-328, (2009)). The prior art vertically integrated silicon wire device was formed by coating the PDMS over the wires and peeling the resultant embedded wire film from the growth substrate using a razor blade. The resultant embedded wire film is flexible and self supporting. The electrodes are then deposited on either side of the wire film. As previously noted, the silicon wires of this prior art example are not nanowires since their diameters are greater than 1 micron.
Solar cell devices structures with vertical silicon nanowires have been investigated by transferring silicon nanowires from the silicon growth substrate to a separate device substrate. These devices have been formed by embedding the silicon nanowires into a polymer matrix on a device substrate by using vertical pressure to push the nanowires into the polymer, and then shearing the nanowires from the growth substrate using a horizontal force (S. Shiu, et al., Proc. of SPIE Vol. 7047, 70470F, (2008)). In one instance nanowires were embedded into a functional polymer to create a hybrid solar cell where the nanowires enhanced the cell's performance (J.-S Huang, et al., So. Energy Mater. Sol. Cells (2009), doi:101.1165/j.solmat.2008.12.016). In the literature structures to date, the nanowires in these types of device structures have direct electrical connection to only one end. These methods are not of particular use to many applications, such as LEDs, since they do not solve the problem of how to make electrical connect to both ends of an array of semiconductor nanowires.
A second prior art vertically integrated semiconductor wire device is shown in FIG. 3. As shown in the figure, a device 260 is formed on a growth substrate 270, over an optional buffer layer 280. The device 260 includes a first electrode is 215, a second electrode is 220, a semiconductor nanowire is 240, and a dielectric 290. The semiconductor nanowires 240 have diameters in the range of 100 to 400 nm. The dielectric 290 can be a polymer or other coatable material such as spin-on-glass (SOG). This device structure requires patterning of the embedded nanowire layer in order to separate the devices and to create an open area on the buffer layer for depositing the second electrode. In order to pattern the embedded nanowire layer, two process steps are required due to the different etch chemistries necessary for the semiconductor and dielectric. The wires of this second prior art example are nanowires, however the device structure fails to solve one of the fundamental problems in forming vertically integrated semiconductor nanowire devices, that of making direct contact to either end of the nanowires.
Consequently, in spite of the technological advances in device architecture and methods, problems remain in generating quality vertically integrated semiconductor nanowire devices.